1 . Field of the Invention
The present invention relates to integrated circuit phase-locked loops, and in particular, to a bias current control circuit for minimization of power consumption.
2 . Discussion of the Related Art
In an integrated circuit, a phase-locked loop, or PLL, is used to track the frequency of an incoming signal and also free the incoming signal from noise. A conventional PLL implementation is shown in FIG. 1. A reference input signal R.sub.-- SIG is provided by a stable oscillator such as a crystal oscillator 109 and a frequency divider 101. Signal R.sub.-- SIG is made up of clock pulses of frequency f.sub.ref, which is defined by:
f.sub.ref =f.sub.c /R PA1 f.sub.N =f.sub.vco /N
where f.sub.c is the crystal frequency and R is the division factor of frequency divider 101. Concurrently, voltage-controlled oscillator a VCO 108 sends a frequency divider 102 a signal V.sub.-- SIG made up of clock pulses of frequency f.sub.vco. Frequency divider 102, having a division factor of N, generates a signal N.sub.-- SIG having a frequency f.sub.N, which is defined by:
A phase comparator 103 compares the relative timing of signal R.sub.-- SIG and signal N.sub.-- SIG, and outputs an error signal P.sub.-- SIG based on their phase and frequency difference. Signal P.sub.-- SIG causes a charge pump 104 to generate pulses that both sink and source current. Current sources 105 and 106 provide charge pump 104 with bias currents required for proper pulse generation. These pulses charge or discharge a loop filter 107, which consequently produces an output voltage Vref. Voltage Vref is applied to VCO 108, which adjusts VCO 108's frequency accordingly. In this manner, f.sub.N is adjusted to match f.sub.ref.
Charge pump 104, current sources 105 and 106, and loop filter 107 can be modeled by the schematic circuit 401 of FIG. 4. As shown in FIG. 4, a current source 402 is coupled to a current mirror 404. When a switch 406 is closed, current flows directly from Vdd to current source 402, without passing through current mirror 404. When switch 406 is opened, a bias current High flows through current mirror 404, charging a loop filter 408. Similarly, a current source 403 is coupled to a current mirror 405. When a switch 407 is closed, current flows directly from current source 403 to ground. When switch 407 is opened, a bias current Ilow flows through current mirror 405, discharging loop filter 408. The voltage on loop filter 408 determines the output frequency of VCO 108. Therefore, the output of phase comparator 103, which controls the activity of switches 406 and 407, actually tunes the frequency of VCO 108.
The use of a current source in combination with a current mirror provides an accurate, rapid-switching output that can be applied to multiple locations. However, the bias currents required for such a configuration can unnecessarily dissipate power in the circuit. As can be seen in FIG. 4, current mirrors 404 and 405 only require a bias current when switches 406 and 407, respectively, are open. In general, switches 406 and 407 are only open for a small percentage of the time, especially when the PLL is phase-locked. At all other times, switches 406 and 407 are closed, meaning that the bias currents from current sources 402 and 403 are simply dissipating energy. An effort to reduce this excess power consumption is demonstrated in co-pending Patent Application NS3341 by Olgaard. The co-pending Patent Application of Olgaard describes a scheme in which a fixed control circuit is implemented to turn on the bias currents only during pre-specified intervals. By turning off bias currents during a portion of the time that bias currents are not needed, total power consumption is reduced. However, the bias current activation intervals must be defined according to the max imum possible charge pump operating frequency, while the charge pump is generally running at much less than maximum frequency. Consequently, the bias currents are still unnecessarily flowing for significant periods of time.
Ac cordingly, it is desirable to provide a bias control circuit that is capable of minimizing bias circuit power consumption by turning on bias currents only when required by charge pump activity.